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Media Alert: Atomera to Present at SISPAD 2023

Atomera Incorporated (Nasdaq: ATOM):


Professor Hiu Yung Wong of San Jose University, Robert J. Mears, CTO, and Hideki Takeuchi, Vice President of Engineering of Atomera Incorporated (Nasdaq: ATOM), a semiconductor materials and technology licensing company




In-person presentation of San Jose State’s and Atomera’s joint poster, entitled

“Cryogenic Electron Mobility and Subthreshold Slope of Oxygen-Inserted (OI) Si Channel nMOSFETs”




Wednesday, September 27 from 11 p.m. – Thursday, September 28 12:30 a.m. PDT

Thursday, September 28 from 3 p.m. – 4:30 p.m. JST




Kobe Chamber of Commerce and Industry (KCCI), Meeting Room 1

6-1 Minatojimanakamachi, Chuo-ku,

Kobe-shi, Hyogo 650-8543, Japan


This poster presentation will discuss the new findings of the physical mechanism of why MST® (also referred to as “Oxygen-inserted”, or “OI Si”, in nMOSFETs channel) provides higher inversion-layer carrier mobility than a regular silicon channel, thus enabling higher ON-state current of CMOS devices compared to the baseline devices. Cryogenic-temperature electron-mobility measurement at San Jose State University revealed that Atomera’s MST film improves surface-roughness scattering by 53% compared to a regular Si channel – a significant result because surface-roughness scattering is typically the dominant mobility barrier in high vertical effective field. In addition, MST improves Coulomb scattering, which is significant at low vertical effective field, by reducing ionized dopant impurities near the gate dielectric. A simple analytical formula to describe the observed mobility behaviors of the MST film has been established for compact modeling.

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About Atomera

Atomera Incorporated, one of America’s top 100 Best Small Companies in 2022 ranked by Forbes, is a semiconductor materials and technology licensing company focused on deploying its proprietary, silicon-proven technology into the semiconductor industry. Atomera has developed Mears Silicon Technology™ (MST®), which increases performance and power efficiency in semiconductor transistors. MST can be implemented using equipment already deployed in semiconductor manufacturing facilities and is complementary to other nano-scaling technologies in the semiconductor industry roadmap. More information can be found at


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